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Obsolete Device
24LC41
1K/4K 2.5V Dual Mode, Dual Port I2CTM Serial EEPROM
Features
* Single supply with operation down to 2.5V * Completely implements DDC1/DDC2 interface for monitor identification * Separate high speed 2-wire bus for microcontroller access to 4K-bit Serial EEPROM * Low-power CMOS technology * 2 mA active current typical * 20 A standby current typical at 5.5V * Dual 2-wire serial interface bus * Hardware write-protect for both ports * Self-timed write cycle (including auto-erase) * Page write buffer for up to 8 bytes (DDC port) or 16 bytes (4K Port) * 100 kHz (2.5V) and 400 kHz (5V) compatibility * 1,000,000 erase/write cycles ensured * Data retention > 40 years * 8-pin PDIP package * Available for extended temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C
Package Type
PDIP DSCL VCLK/DWP VSS MSDA 1 2 3 4 24LC41 8 7 6 5 DSDA
VCC
MWP MSCL
Block Diagram
DSDA EDID Table 1K Bit VCLK/DWP DSCL Microcontroller Access Port MSDA 4K Bit Serial EEPROM DDC Monitor Port
MSCL
Description
The Microchip Technology Inc. 24LC41 is a dual-port 128 x 8 and 512 x 8-bit Electrically Erasable PROM (EEPROM). This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Three modes of operation have been implemented: * Transmit-only mode for the DDC Monitor Port * Bidirectional mode for the DDC Monitor Port * Bidirectional, industry-standard 2-wire bus for the 4K Microcontroller Access Port Upon power-up, the DDC Monitor Port will be in the Transmit-only mode, repeatedly sending a serial bit stream of the entire memory array contents, clocked by the VCLK/DWP pin. A valid high-to-low transition on the DSCL pin will cause the device to enter the Bidirectional mode, with byte-selectable read/write capability of the memory array. The 4K-bit microcontroller port is completely independent of the DDC port, therefore, it can be accessed continuously by a microcontroller without interrupting DDC transmission activity. The 24LC41 is available in a standard 8-pin PDIP package in both commercial and industrial temperature ranges.
MWP
I2C is a registered trademark of Philips Corporation.
2004 Microchip Technology Inc.
DS21140F-page 1
24LC41
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-65C to +125C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
VCC = +2.5V to 5.5V Commercial (C): TA = 0C to +70C Industrial (I): TA = -40C to +85C Symbol VIH VIL VIH VIL VHYS VOL1 VOL2 ILI ILO CIN, COUT ICC Write ICC Read ICCS Min .7 VCC -- Max -- .3 VCC Units V V V V V V V A A pF mA mA A A VCC 2.7V (Note) VCC < 2.7V (Note) (Note) IOL = 3 mA, VCC = 2.5V (Note) IOL = 6 mA, VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note), TA = 25C, FCLK = 1 MHz VCC = 5.5V, DSCL or MSCL = 400 kHz VCC = 3.0V, DSDA or MSDA = DSCL or MSCL = VCC VCC = 5.5V, DSDA or MSDA = DSCL or MSCL = VCC VCLK = VSS Conditions
DC CHARACTERISTICS Parameter DSCL, DSDA, MSCL & MSDA pins: High-level input voltage Low-level input voltage Input levels on VCLK/DWP pin: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current
2.0 .8 -- .2 VCC .05 VCC -- -- .4 -- .6 -- 1 -- 1 -- 10 -- -- -- -- 3 1 60 200
Note:
This parameter is periodically sampled and not 100% tested.
DS21140F-page 2
2004 Microchip Technology Inc.
24LC41
TABLE 1-2: AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)
DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port Standard Mode Parameter Clock frequency (DSCL and MSCL) Clock high time (DSCL and MSCL) Clock low time (DSCL and MSCL) DSCL, DSDA, MSCL and MSDA rise time DSCL, DSDA, MSCL and MSDA fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time Symbol Min FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc = 4.5 - 5.5V Fast Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition (Note 2)
Units
Remarks
Output fall time from VIH -- 250 TOF min to VIL max -- 50 Input filter spike TSP suppression (DSCL, DSDA, MSCL and MSDA pins) -- 10 Write cycle time TWR DDC Monitor Port Transmit-Only Mode Parameters Output valid from VCLK/ DWP VCLK/DWP high time VCLK/DWP low time Mode transition time Transmit-only power-up time Endurance Note 1: 2: TVAA TVHIGH TVLOW TVHZ TVPU -- -- 4000 4700 -- 0 1M 2000 -- -- 500 -- --
20 + .1 CB --
250 50
ns ns
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
-- -- 600 1300 -- 0 1M
10 1000 -- -- 500 -- --
ms ns ns ns ns ns cycles
Byte or Page mode
25C, Vcc = 5.0V, Block mode (Note 4)
3: 4:
Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM model which can be obtained from our web site.
2004 Microchip Technology Inc.
DS21140F-page 3
24LC41
2.0
2.1
FUNCTIONAL DESCRIPTION
DDC Monitor Port
The DDC Monitor Port operates in two modes, the Transmit-only mode and the Bidirectional mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input and sharing a common data line (DSDA). The device enters the Transmit-only mode upon power-up. In this mode, the device transmits data bits on the DSDA pin in response to a clock signal on the VCLK/DWP pin. The device will remain in this mode until a valid high-to-low transition is placed on the DSCL input. When a valid transition on DSCL is recognized, the device will switch into the Bidirectional mode. The only way to switch the device back to the Transmit-only mode is to remove power from the device.
"Initialization Procedure"). In this mode, data is transmitted on the DSDA pin in 8-bit bytes, each followed by a ninth, null bit (Figure 2-1). The clock source for the Transmit-only mode is provided on the VCLK/DWP pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted by Most Significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The Bidirectional mode Clock (DSCL) pin must be held high for the device to remain in the Transmit-only mode.
2.3
Initialization Procedure
2.2
Transmit-Only Mode
The device will power-up in the Transmit-only mode. This mode supports a unidirectional 2-wire protocol for transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Transmit-only mode (Section 2.3
After VCC has stabilized, the device will be in the Transmit-only mode. Nine clock cycles on the VCLK/ DWP pin must be given to the device for it to perform internal sychronization. During this period, the DSDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit of a byte. The device will power-up at an indeterminate byte address (Figure 2-2).
FIGURE 2-1:
DSCL
TRANSMIT-ONLY MODE
TVAA
TVAA
DSDA Bit 1 (LSB)
Null Bit Bit 1 (MSB) Bit 7
VCLK/DWP TVHIGH TVLOW
FIGURE 2-2:
VCC SCL
DEVICE INITIALIZATION
TVAA
TVAA
SDA
High-impedance for 9 clock cycles TVPU
Bit 8
Bit 7
VCLK/DWP
1
2
8
9
10
11
DS21140F-page 4
2004 Microchip Technology Inc.
24LC41
2.3.1 BIDIRECTIONAL MODE
2.4
Microcontroller Access Port
The DDC Monitor Port can be switched into the Bidirectional mode (Figure 2-3) by applying a valid high-to-low transition on the Bidirectional mode Clock (DSCL). When the device has been switched into the Bidirectional mode, the VCLK/DWP input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a 2-wire bidirectional data transmission protocol. In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bidirectional mode Clock (DSCL), controls access to the bus and generates the Start and Stop conditions, while the DDC Monitor Port acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
The Microcontroller Access Port supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (MSCL), controls the bus access, and generates the Start and Stop conditions, while the Microcontroller Access Port works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
FIGURE 2-3:
MODE TRANSITION
Transmit-only Mode Bidirectional Mode
DSCL
TVHZ
DSDA
VCLK/DWP
2004 Microchip Technology Inc.
DS21140F-page 5
24LC41
3.0 BIDIRECTIONAL BUS CHARACTERISTICS
3.5 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The microcontroller access port and the DDC Monitor Port (in Bidirectional mode) will not generate any Acknowledge bits if an internal programming cycle is in progress.
Characteristics for the bidirectional bus are identical for both the DDC Monitor Port (in Bidirectional mode) and the Microcontroller Access Port The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
The device that acknowledges has to pull down the DSDA or MSDA line during the Acknowledge clock pulse in such a way that the DSDA or MSDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition.
A high-to-low transition of the DSDA or MSDA line while the clock (DSCL or MSCL) is high determines a Start condition. All commands must be preceded by a Start condition.
3.6
Device Addressing
3.3
Stop Data Transfer (C)
A low-to-high transition of the DSDA or MSDA line while the clock (DSCL or MSCL) is high determines a Stop condition. All operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion.
A control byte is the first byte received following the Start condition from the master device. The first part of the control byte consists of a 4-bit control code. This control code is set as 1010 for both read and write operations and is the same for both the DDC Monitor Port and Microcontroller Access Port. The next three bits of the control byte are block select bits (B1, B2 and B0). All three of these bits are don't care bits for the DDC Monitor Port. The B2 and B1 bits are don't care bits for the Microcontroller Access Port, and the B0 bit is used by the Microcontroller Access Port to select which of the two 256 word blocks of memory are to be accessed (Figure 3-4). The B0 bit is effectively the Most Significant bit of the word address. The last bit of the control byte defines the operation to be performed. When set to one, a read operation is selected; when set to zero, a write operation is selected. Following the Start condition, the device monitors the DSDA or MSDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the device will select a read or a write operation. The DDC Monitor Port and Microcontroller Access Port can be accessed simultaneously because they are completely independent of one another. Operation Read Write Control Code 1010 1010 Chip Select XXB0 XXB0 R/W 1 0
DS21140F-page 6
2004 Microchip Technology Inc.
24LC41
FIGURE 3-1:
DSCL or MSCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
DSDA or MSDA
Start Condition
Address or Acknowledge Valid
Data Allowed to Change
Stop Condition
FIGURE 3-2:
BUS TIMING START/STOP
VHYS
MSCL or MSCL IN DSDA or MSDA IN
TSU:STA
THD:STA TSU:STO
Start
Stop
FIGURE 3-3:
BUS TIMING DATA
TF THIGH TLOW TR
DSCL or MSCL TSU:STA IN
DSDA
OR
THD:DAT THD:STA TSP TAA THD:STA
TSU:DAT
TSU:STO
MSDA IN
TAA
TBUF
DSDA
OR
MSDA OUT
FIGURE 3-4:
CONTROL BYTE ALLOCATION
Start READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
X = Don't care. B0 is don't care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256 word blocks of memory are to be accessed.
2004 Microchip Technology Inc.
DS21140F-page 7
24LC41
4.0 WRITE OPERATION
4.2 Page Write
Write operations are identical for the DDC Monitor Port (when in Bidirectional mode) and the Microcontroller Access Port, with the exception of the VCLK/DWP and MWP pins noted in the next sections. Data can be written using either a Byte Write or Page Write command. Write commands for the DDC Monitor Port and the Microcontroller Access Port are completely independent of one another. The write control byte, word address, and the first data byte are transmitted to the port in the same way as in a byte write. But, instead of generating a Stop condition, the master transmits up to eight data bytes to the DDC Monitor Port or 16 bytes to the Microcontroller Access Port, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order 5-bits of the word address remains constant. If the master should transmit more than eight words to the DDC Monitor Port or 16 words to the Microcontroller Access Port prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-2). For the DDC Monitor Port, it is required thatVCLK/ DWP be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK/DWP can go low while the device is in its self-timed program operation and not affect programming. For the Microcontroller Access Port, the MWP pin must be held to VSS during the entire write operation.. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
4.1
Byte Write
Following the Start signal from the master, the slave address (4-bits), the Chip Select bits (3-bits) and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the port. After receiving another Acknowledge signal from the port, the master device will transmit the data word to be written into the addressed memory location. The port acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time, the port will not generate Acknowledge signals (Figure 4-1). For the DDC Monitor Port it is required that VCLK/DWP be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK/DWP can go low while the device is in its self-timed program operation and not affect programming. For the Microcontroller Access Port, the MWP pin must be held to VSS during the entire write operation.
DS21140F-page 8
2004 Microchip Technology Inc.
24LC41
FIGURE 4-1:
Bus Activity Master S T A R T
BYTE WRITE
Control Byte Word Address Data S T O P
SDA or MSDA Line
S
A C K A C K A C K
P
Bus Activity VCLK
FIGURE 4-2:
Bus Activity Master
PAGE WRITE
S T A R T S T O P
Control Byte
Word Address
Data n
Data n + 1
Data n + 15
SDA LINE
S
A C K A C K A C K A C K A C K
P
Bus Activity VCLK/DWP
2004 Microchip Technology Inc.
DS21140F-page 9
24LC41
5.0 ACKNOWLEDGE POLLING 6.0
6.1
WRITE PROTECTION
DDC Monitor Port
Acknowledge polling can be done for both the DDC Monitor Port (when in Bidirectional mode) and the Microcontroller Access Port. Since the port will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize but throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for the flow diagram.
When using the DDC Monitor Port in the Bidirectional mode, the VCLK/DWP pin operates as the write-protect control pin. Setting VCLK/DWP high allows normal write operations, while setting VCLK/DWP low prevents writing to any location in the array. Connecting the VCLK/DWP pin to VSS would allow the DDC Monitor Port to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-only mode.
6.2
Microcontroller Access Port
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The Microcontroller Access Port can be used as a serial ROM when the MWP pin is connected to VCC. Programming will be inhibited and the entire memory associated with the Microcontroller Access Port will be write-protected.
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
DS21140F-page 10
2004 Microchip Technology Inc.
24LC41
7.0 READ OPERATION
7.3 Sequential Read
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. These operations are identical for both the DDC Monitor Port (in Bidirectional mode) and the Microcontroller Access Port and are completely independent of one another. Sequential reads are initiated in the same way as a random read except that after the port transmits the first data byte, and the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the port to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads, the port contains an internal address pointer, which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.
7.1
Current Address Read
The port contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the port issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the port discontinues transmission (Figure 7-1).
7.4
Noise Protection
Both the DDC Monitor Port and Microcontroller Access Port employ a VCC threshold detector circuit which disables the internal erase/write logic, if the VCC is below 1.5 volts at nominal conditions. The DSCL, MSCL, DSDA and MSDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
7.2
Random Read
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the port as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The master then issues the control byte again, but with the R/W bit set to a one. The port then issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the port discontinues transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
Bus Activity Master
S T A R T Control Byte S T O P
Data n
DSDA or MSDA Line
S
A C K N O A C K
P
BUS Activity
2004 Microchip Technology Inc.
DS21140F-page 11
24LC41
FIGURE 7-2: RANDOM READ
S T A R T Control Byte Word Address S T A R T Control Byte S T O P
Bus Activity Master
MSDA Line
Data n
S
A C K A C K
S
A C K N O A C K
P
Bus Activity
FIGURE 7-3:
SEQUENTIAL READ
Control Byte
S T O P
Bus Activity Master
DSDA or MSDA Line
Data n
Data n + 1
Data n + 2
Data n + X
P
A C K A C K A C K A C K N O A C K
Bus Activity
DS21140F-page 12
2004 Microchip Technology Inc.
24LC41
8.0 PIN DESCRIPTIONS
8.3 VCLK/DWP
The descriptions of the pins are listed in Table 8-1. This pin is the clock input for the DDC Monitor Port while in the Transmit-only mode. In the Transmit-only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability.
TABLE 8-1:
Name DSCL DSDA VCLK/DWP MSCL MSDA MWP VSS VCC
PIN FUNCTION TABLE
Function Serial Clock for DDC Bidirectional mode (DDC2) Serial Address and Data I/O (DDC Bus) Serial Clock for DDC Transmit-only mode (DDC1)/Write-Protect Serial clock for 4 Kbit MCU port Serial Address and Data I/O for 4 Kbit MCU port Hardware write-protect for 4 Kbit MCU port Ground +2.5V to +5.5V power supply
8.4
MSCL
This pin is the clock input for the Microcontroller Access Port, and is used to synchronize data transfer to and from the device.
8.5
MSDA
This pin is used to transfer addresses and data into and out of the Microcontroller Access Port. This pin is an open drain terminal, therefore the MSDA bus requires a pull-up resistor to VCC (typical 10K for 100 kHz, 2K for 400 kHz). MSDA is allowed to change only during MSCL low. Changes during MSCL high are reserved for indicating the Start and Stop conditions.
8.1
DSDA
This pin is used to transfer addresses and data into and out of the DDC Monitor Port, when the device is in the Bidirectional mode. In the Transmit-only mode, which only allows data to be read from the device, data is also transferred on the DSDA pin. This pin is an open drain terminal, therefore the DSDA bus requires a pull-up resistor to VCC (typical 10K for 100 kHz, 2 K for 400 kHz). For normal data transfer in the Bidirectional mode, DSDA is allowed to change only during DSCL or MSDA low. Changes during DSCL high are reserved for indicating the Start and Stop conditions.
8.6
MWP
This pin is used to write-protect the 4K memory array for the Microcontroller Access Port. This pin must be connected to either VSS or VCC. If tied to Vss, normal memory operation is enabled (read/write the entire memory). If tied to VCC, Write operations are inhibited. The entire memory will be write-protected. Read operations are not affected.
8.2
DSCL
This pin is the clock input for the DDC Monitor Port while in the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-only mode to the Bidirectional mode. It must remain high for the chip to continue operation in the Transmit-only mode.
2004 Microchip Technology Inc.
DS21140F-page 13
24LC41
APPENDIX A:
Revision E Corrections to Section 1.0, Electrical Characteristics.
REVISION HISTORY
DS21140F-page 14
2004 Microchip Technology Inc.
24LC41
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern
Device
24LC41 Dual Mode, Dual Port I2C Serial EEPROM
Temperature Range
Blank I
= 0C to = -40C to
+70C +85C
Package
P
=
PDIP
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21140F-page 15
24LC41
NOTES:
DS21140F-page 16
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21140F-page 17
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com
China - Beijing
Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104
Singapore
200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4816 Fax: 886-7-536-4817
China - Chengdu
Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Taiwan
Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Fuzhou
Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
Taiwan
Taiwan Branch 13F-3, No. 295, Sec. 2, Kung Fu Road Hsinchu City 300, Taiwan Tel: 886-3-572-9526 Fax: 886-3-572-6459
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Dallas
16200 Addison Road, Suite 255 Addison Plaza Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
EUROPE
Austria
Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
China - Shanghai
Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Denmark
Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393
Kokomo
2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
China - Shunde
Room 401, Hongjian Building, No. 2 Fengxiangnan Road, Ronggui Town, Shunde District, Foshan City, Guangdong 528303, China Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
25950 Acero St., Suite 200 Mission Viejo, CA 92691 Tel: 949-462-9523 Fax: 949-462-9608
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Germany
Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
San Jose
1300 Terra Bella Avenue Mountain View, CA 94043 Tel: 650-215-1444 Fax: 650-961-0286
India
Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-22290061 Fax: 91-80-22290062
Italy
Via Salvatore Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Japan
Yusen Shin Yokohama Building 10F 3-17-2, Shin Yokohama, Kohoku-ku, Yokohama, Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Netherlands
Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Unit 32 41 Rawson Street Epping 2121, NSW Sydney, Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
United Kingdom
505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820
07/12/04
2004 Microchip Technology Inc.

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